By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complicated recommendations and strategies used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the complete ASIC layout circulation method special for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time software of Synopsys instruments used to strive against numerous difficulties noticeable at VDSM geometries. Readers can be uncovered to a good layout technique for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, and static timing research. At each one step, difficulties on the topic of each one part of the layout stream are pointed out, with recommendations and work-arounds defined intimately. furthermore, an important matters relating to structure, together with clock tree synthesis and back-end integration (links to format) also are mentioned at size. additionally, the e-book includes in-depth discussions at the fundamentals of Synopsys know-how libraries and HDL coding kinds, detailed in the direction of optimum synthesis options.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for somebody who's concerned about the ASIC layout technique, ranging from RTL synthesis to ultimate tape-out. objective audiences for this e-book are working towards ASIC layout engineers and graduate scholars project complicated classes in ASIC chip layout and DFT strategies.
From the Foreword:
`This booklet, written by means of Himanshu Bhatnagar, presents a entire assessment of the ASIC layout circulation precise for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible matters confronted through the semiconductor layout engineer when it comes to synthesis and the mixing of front-end and back-end instruments. conventional layout methodologies are challenged and targeted ideas are provided to assist outline the following iteration of ASIC layout flows. the writer offers a variety of useful examples derived from real-world occasions that may turn out beneficial to training ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant platforms, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Additional info for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
If the design fails the hold-time requirements then you should fix the violations by adding buffers to delay the arrival time of the failing signals, with respect to the clock. Let's assume that the design is failing hold-time requirements at multiple endpoints. There are various approaches to fix the hold-time violations. Such methods are discussed in detail in Chapter 9. t. sv" In the above script, the set_fix_hold command instructs DC to fix hold-time violations with respect to the clock tck.
Db library. 3 SDF Generation To perform timing simulation, you will need the SDF file for back annotation. The static timing was performed using PT; therefore it is prudent that the SDF file be generated from PT itself. However, most designers feel comfortable in using DC to generate the SDF file. We will therefore use DC to generate the SDF in this section. 27 TUTORIAL Depending on the design, the resultant SDF file may require a certain amount of "massaging" before it can be used to perform timing simulation of the design.
The static timing was performed using PT; therefore it is prudent that the SDF file be generated from PT itself. However, most designers feel comfortable in using DC to generate the SDF file. We will therefore use DC to generate the SDF in this section. 27 TUTORIAL Depending on the design, the resultant SDF file may require a certain amount of "massaging" before it can be used to perform timing simulation of the design. The reason for massaging is explained in detail in Chapter 10. The previous section described a method of defining the clock latency and transition in PT.